1. Field of the Invention
The present invention relates to a microprocessor incorporating peripheral devices and, more particularly, to a microprocessor having a functionally multiplexed input and output terminal.
2. Related Art
A microprocessor is known in which peripheral and control devices such as a ROM, a RAM, a serial interface, a timer, an interrupt controller, and a port are integrated with a CPU (Central Processing Unit) on a semiconductor substrate. In a conventional microprocessor, a terminal is often shared (multiplexed) by a peripheral device and an input and output port (I/O port).
An example where a pulse circuit and an I/O port share the terminal will now be described, with reference to FIGS. 3 through 7C. FIG. 3 shows an internal arrangement of a microprocessor where the pulse circuit and the I/O port share the input and output (I/O) terminal. This microprocessor is provided with an internal bus 1, a port mode control register 2, a port mode register 3, a port register 4, a pulse generator 5, an I/O terminal 6, an input terminal 7, a selector 8, an NAND gate 9, and an inverter 10 for data input, an OR gate 11, a three-state buffer 12, and gates G1 through G5.
The port mode control register 2 is used to set the I/0 terminal 6 in a port mode (a mode in which the I/O terminal 6 serves as an I/O port terminal) or a pulse-output mode (a mode in which the I/O terminal 6 serves as an output terminal for the pulse generator 5). When an output of the port mode control register 2 is logic "0" and "1", the I/O terminal 6 is set in the port mode and the pulse output mode, respectively.
The port mode register 3 is used to designate an input mode or an output mode in units of bits when the I/O terminal 6 is set in the port mode. Each bit in the port mode register represents the output mode at logic "0" and the input mode at logic "1".
The port register 4 holds data to be output externally. The pulse generator 5 has an arrangement which is described later with reference to FIG. 4, and generates pulses having arbitrary pulse widths at arbitrary intervals.
The I/O terminal 6 serves both as an I/O terminal of the I/O port and the pulse output terminal of the pulse generator 5. The input terminal 7 receives a trigger signal to be supplied to the pulse generator 5. The selector 8 supplies an output from the port register 4 and an output from the pulse generator 5 to the buffer 12 when the output of the port mode control register 2 is logic "0" and logic "1", respectively.
The AND gate 9 and the inverter 10 transmits a signal externally applied to the I/O terminal 6 to the internal bus 1 through the gate G3. The OR gate 11 applies an output of logic "1" to a control terminal of the three-state buffer 12 when an output of the port mode control register 2 is logic "1" or when an output of the mode register 3 is logic "0", and applies an output of logic "0" to the control terminal of the three-state buffer 12 when an output of the port mode control register 2 is logic "0" and an output of the mode register 3 is logic "1". The three-state buffer 12 serves as a buffer when the signal applied to the control terminal is logic "1", and is set in a high-impedance (open) state when the signal applied to the control terminal is logic "0".
The control terminals of the gates G1 through G5 receive a write signal 20, a write signal 21, a read signal 22, a write signal 23, and a read/write signal 24, respectively. The write signals 20, 21, and 23 open the gates G2 and G4 to write data in the port mode control register 2, the port mode register 3, and port register 4, respectively. The read signal 22 opens the gate G3 to read data externally supplied through the I/O terminal 6.
The read/write signal 24 opens the gate G5 to write data into or read data from a plurality of registers in the pulse generator 5.
As shown in FIG. 4, the pulse generator 5 comprises a timer 50, compare registers 51 and 52, and a RS flip-flop 53. An output from the flip-flop 53 is supplied to the input terminal 7. When a trigger signal is supplied to the input terminal 7, the timer 50 initiates counting clock pulses O. When a count value of the timer 50 reaches a preset value in the compare register 51, the output of the compare register 51 sets the flip-flop 53. As a result, a Q output of the flip-flop 53 assumes logic "1". When the count value of the timer 50 reaches a preset value in the compare register 52, the output of the compare register 52 resets the flip-flop 53. Thus, the Q output of the flip-flop 53 assumes logic "0".
An operation of the microprocessor shown in FIGS. 3 and 4 will now be described, with reference to FIGS. 5A through 5C.
When the I/O terminal 6 is used in the output mode, a control section not shown controls the write signal 20 to open the gate G1 and sets data "0" in the port mode control register 2, controls the write signal 21 to open the gate G2 and sets data "0" in the mode register 3, controls the write signal 23 to open the gate G4, and sets desired output data in the port register 4.
The OR gate 11 outputs a logic "1" signal to turn on the buffer 12. The selector 8 supplies an output from the port register 4 to the buffer 12. As a result, the output data set in the port register 4 is output through the I/O terminal 6.
When the I/O terminal 6 is used in the input mode, the control section (not shown) controls the write signal 20 to open the gate G1, sets data "0" in the port mode control register 2, and controls the write signal 21 to open the gate G2 and sets data "1" in the mode register 3. The OR gate 11 outputs a logic "0" signal to set the buffer 12 in the open state. The control section sets the read signal to logic "1" to open the AND gate 9 and the gate G3. Then, data supplied externally through the I/O terminal 6 is transmitted to the internal bus 1 through the AND gate 9, the inverter 10, and the gate G3.
When the I/O terminal 6 is used in the pulse output mode, the control section (not shown) controls the write signal 20 to open the gate G1 and sets data "1" in the port mode control register, controls the read/write signal 24 to open the gate G5, and sets values in the compare registers 51 and 52. The OR gate 11 outputs a logic "1" signal to turn on the buffer 12, and the selector 8 selects an output from the pulse generator 5. In this state, when the trigger signal, as shown in FIG. 5B, is supplied to the terminal 7, the timer 50 initiates counting of the clock pulse O. The counted value gradually increases, as shown in FIG. 5A. When the counted value of the timer 50 reaches a preset value in the compare register 51, the flip-flop 53 is set and its Q output becomes logic "1", as shown in FIG. 5C. Further, when the counted value of the timer 50 reaches a preset value in the compare register 52, its Q output becomes logic "0".
Normally, a pulse signal is output from the I/O terminal 6 in the above described manner. However, there is a case where the voltage of the terminal 6 must be fixed at a high or low level independent of the state of the output pulse due to causes such as a system operation and a program execution.
FIGS. 6A through 6C and 7A through 7C show an example where a voltage of the terminal 6 is fixed at a high level. FIGS. 6A through 6C show a case where the pulse output from the terminal 6 remains at a high level independent of the externally supplied trigger signal, and FIGS. 7A through 7C show a case where the pulse output from the terminal 6 remains at a high level until the subsequent trigger signal is output. It should be noted that in FIGS. 6C and 7C, the solid line represents a voltage of the terminal 6, and a broken line represents the output of the pulse generator 5.
An operation for fixing the voltage of the terminal 6 is performed as follows:
First, the control section writes desired data in the port register 4, writes data "0" in the port mode control register 2 to set the port mode, and writes data "0" in the port mode register 3 to set the output mode. The above method is described in detail in the user's manual of the single chip microcomputer 78K/III or 78K/VI available from NEC Corporation (Registered Trademark), Japan.
As described above, in order for the control section to directly control the voltage of the functionally multiplexed terminal, predetermined data must be written in the port mode control register 2 and the port mode register 3 so as to change the mode of the terminal 6 from the pulse output mode to the output port mode. Further, the desired data must be written in the port register 4. These operations are cumbersome and time-consuming, with the result that it is difficult to switch the multiplexed function at high speed.